Arm’s AGI CPU, first announced earlier this year as its first data-center-class processor, is now slated for commercial shipments starting in late 2026. At Hot Chips this week, the company filled in key specifications it had previously withheld, including core counts, clock speeds, cache hierarchy, and memory bandwidth.
The processor is built from two chiplets fabricated on TSMC’s N3P process, each containing 50 billion transistors and 70 Neoverse V3 cores. Configurations will offer 64, 128, or 136 active cores per package. Each core features a 10-wide front end and decode, 10-wide dispatch, 8-wide retire, and a 384+ entry out-of-order window. Cores run at 2.80 GHz to 3.70 GHz and include 2 MB of dedicated L2 cache. A distributed system-level cache of up to 272 MB (128 MB per chiplet) sits on an 8×9 CMN-S3 mesh interconnect.
Memory support is a standout feature: each chiplet integrates a six-channel DDR5 controller, enabling up to 3 TB of DDR5-8800 per chiplet (6 TB per socket) and an aggregate memory bandwidth of 844.8 GB/s. Arm claims DRAM latency can be kept under 100 nanoseconds—a critical factor for latency-sensitive workloads such as single-threaded applications and agentic AI inference.
Arm opted not to follow the heterogeneous multi-chiplet pattern used by AMD, Intel, and Nvidia, where compute chiplets and I/O chiplets are separate. Instead, each AGI chiplet is a complete SoC with its own memory controllers and I/O. The inter-chiplet connection uses 16×16 UCIe macros running at 32 GT/s, delivering an aggregate bandwidth of 2 TB/s. The CPU also provides 96 PCIe 6.0 lanes with CXL 3.0 support, plus four PCIe 4.0 lanes and other standard interfaces. Thermal design power is rated at 300W.
Arm said the AGI processor is already working as expected and that the company is on track for commercial shipments in the coming months. The detailed disclosure at Hot Chips suggests the design is mature enough to share with potential customers and partners.