Fujitsu detailed its 144-core Monaka server CPU at Hot Chips 2026 on August 24, confirming the Arm-based chip runs dual 256-bit SVE2 vector units and stacks its entire last-level cache on a separate 5nm die beneath a 2nm compute die. Evaluation samples are available now, with volume production scheduled for 2027.
Fujitsu gave a detailed look at its 144-core Monaka server CPU at Hot Chips 2026 on August 24, confirming for the first time that the Arm-based chip runs dual 256-bit SVE2 vector units — down from the 512-bit SVE in its A64FX predecessor — and that its entire last-level cache sits on a separate 5nm die beneath the 2nm compute die.
Ryohei Okazaki, lead architect of Fujitsu's processor development team, described the design as "a made-in-Japan CPU, specifically engineered for AI performance and power efficiency," built for what the company calls green AI data centers. The project is subsidized by Japan's New Energy and Industrial Technology Development Organization (NEDO).
Monaka ships in two SKUs: a 350W air-cooled part with a 2.1 GHz base clock and a 500W liquid-cooled part at 2.9 GHz base. Evaluation samples are available now, with volume production slated for 2027.
Three dies, one stack
Monaka splits into three tiers of silicon: a 2nm core die on TSMC N2P, a 5nm SRAM die on TSMC N5 that holds the entire last-level cache, and a 5nm IO die. The core die stacks face-to-face on top of the SRAM die through hybrid bonding, sitting on the cooling side because it runs hottest. The IO die connects to the SRAM die across a silicon interposer.
Fujitsu keeps 2nm silicon under 30% of total die area — a split Okazaki said lets the company "accelerate the time to market for our 2-nanometer-based chip" by pushing everything that shrinks poorly onto the 5nm SRAM and IO dies. Fujitsu also moved low-dropout voltage regulators onto the 5nm SRAM die because analog circuits scale poorly at 2nm, placing them directly beneath the core's floating-point units to feed per-core dynamic voltage and frequency scaling.
The approach separates Monaka from AMD's 3D V-Cache, which bonds extra SRAM on top of a compute die that already carries its own L3, and lines it up more closely with Intel's Clearwater Forest, where local cache sits in a base tile with compute stacked above.
Narrower vectors, smaller cores
Chester Lam of Chips and Cheese asked why Fujitsu narrowed the vector datapath from 512-bit SVE to 256-bit SVE2. Okazaki said the chip is built "for [the] data center" and that Fujitsu wanted to "minimize the core size" for the best cost and performance, with the narrower units also cutting SIMD width for general-purpose code.
Dr. Ian Cutress of More Than Moore asked whether Fujitsu was "doing anything special to minimize core-to-core latency" given that core dies sit on opposite sides of the package and traffic routes through the IO die and back. Fujitsu pointed to the face-to-face hybrid bonding between the core and SRAM dies but declined to disclose latency figures.
Analysis
Why This Matters
- Monaka is a state-backed bet that Japan can field a competitive AI-era server CPU, pairing NEDO subsidies with a power-efficiency-first design for "green" data centers.
- The 2nm/5nm split-die approach could become a template for managing the cost and yield challenges of leading-edge nodes, putting only logic that benefits from 2nm on that node.
- With volume production in 2027, Monaka enters a data center market crowded with AMD EPYC, Intel Xeon, and Nvidia's Arm-based Grace-class parts.
Background
Fujitsu's previous server CPU, the A64FX, powered the Fugaku supercomputer, which repeatedly topped the TOP500 list between 2020 and 2022 and used 512-bit SVE vector units paired with HBM memory. Monaka is a deliberate departure: it targets AI and general data center workloads rather than HPC simulation, and trades the wider SVE design for a narrower 256-bit SVE2 datapath to reduce core size and cost.
The chip also reflects Japan's broader push for semiconductor self-reliance. NEDO, the government agency that backed Monaka's development, has funded multiple domestic chip projects as Japan seeks to rebuild advanced manufacturing and design capabilities. Fujitsu is using TSMC's N2P process for the compute die — an indication of the foundry model now embedded in Japan's chip strategy.
At Hot Chips, presenters drew contrasts with AMD's 3D V-Cache, where extra SRAM is stacked directly atop a compute die that already contains L3 cache, and Intel's Clearwater Forest, which places cache in a base tile beneath the compute dies. Monaka's decision to move the entire last-level cache to a separate stacked die is among the most aggressive versions of that idea.
Key Perspectives
Fujitsu (Ryohei Okazaki): The split-die design accelerates time to market by limiting 2nm silicon to under 30% of total die area, and the narrower vector units minimize core size for data center cost-performance. The company emphasizes AI performance and power efficiency for green data centers.
Industry analysts (Dr. Ian Cutress, More Than Moore; Chester Lam, Chips and Cheese): They pressed Fujitsu on architectural trade-offs — core-to-core latency across dies and the reduction from 512-bit to 256-bit vector width — areas where the company declined to give full details.
Competing vendors (AMD, Intel): Monaka enters a market where AMD's 3D V-Cache and Intel's Clearwater Forest base-tile designs pursue similar stacking goals through different packaging choices. The absence of published benchmark or latency data makes direct comparison difficult until silicon ships in volume.
What to Watch
- Whether Fujitsu discloses core-to-core latency figures or benchmark results as evaluation samples reach partners.
- The 2027 volume production timeline — any slip could cede ground to Intel's 18A ramp and AMD's next-generation EPYC.
- Adoption signals: which Japanese data center operators or cloud providers commit to Monaka-based systems, and how pricing compares against Grace and EPYC.