Samsung outlined its vision for the future of high-bandwidth memory at the Hot Chips 2026 conference, describing a three-phase evolution that moves HBM from a passive data conduit to an active participant in computation. The company's Sangwook Han of the DRAM design team identified the base die as the key enabler, beginning with Samsung's decision to manufacture the HBM4 base die on a 4nm logic process rather than a DRAM process.
In conventional HBM, multiple DRAM core dies are stacked vertically on a base die and connected via thousands of through-silicon vias (TSVs). The stack sits beside an XPU on a 2.5D interposer, with the base die bridging memory and compute. Current HBM4 stacks offer roughly 1 to 5 TB/s of bandwidth using 1,024 to 2,048 data I/Os running at 8–16 Gbps each. However, scaling bandwidth by adding more TSVs or increasing signaling speed consumes area, forces tighter pitches, and drives up power consumption — the total HBM power continues to rise even as energy per bit improves.
Phase 1: Reclaim XPU Area
The first phase focuses on reducing the physical footprint of memory interfaces on the accelerator die. Samsung proposes moving the HBM Physical Interface (PHY) — one of the largest non-compute blocks on the XPU — onto the base die, replacing the traditional interface with a much smaller die-to-die (D2D) link. This frees up valuable silicon area on the XPU for additional compute logic, helping to overcome reticle and interposer limits.
Phase 2: Active Memory
In the second phase, the base die gains more processing capabilities, transitioning from a simple interface to performing data-intensive operations such as near-memory compute. This approach reduces data movement between memory and the XPU, lowering latency and power consumption. The exact functions to be offloaded remain under development, but Samsung envisions the base die handling tasks like data filtering, compression, or simple arithmetic.
Phase 3: zHBM — Stacking DRAM Directly on the Processor
The final phase, called zHBM, eliminates the physical gap between DRAM and the XPU altogether. The entire DRAM stack is placed directly on top of the processor, removing the need for a 2.5D interposer. By stacking memory vertically over compute, zHBM dramatically shortens interconnect distances, potentially offering orders-of-magnitude improvements in bandwidth density and energy efficiency. Samsung debuted zHBM as part of its next-generation memory technologies for AI data centers, relying on advanced wafer bonding techniques.
Samsung refers to the broader strategy as "custom HBM" (cHBM), where the base die is tailored for a specific accelerator while keeping the standard DRAM stack. The roadmap underscores a growing industry push to overcome the "memory wall" by embedding intelligence within the memory hierarchy.