TSMC confirms High-NA EUV adoption for 2030, targeting A10 and A11 nodes

TSMC's announcement this week marks a significant shift in the company's lithography roadmap. For years, the Taiwanese chipmaker had refrained from detailing its High-NA EUV plans, indicating that its developers believed they could extend process technology advancements without the costly scanners. However, the company acknowledged that it cannot rely on Low-NA EUV systems indefinitely.

Under the plan, TSMC will first use High-NA EUV tools with conventional 6×6-inch photomasks in 2030, achieving an 8nm single-exposure resolution compared to 13nm with current Low-NA EUV systems. A pilot line using 6×12-inch photomasks is scheduled for 2031, with full production on the larger masks targeted for 2033.

The transition to 6×12-inch photomasks is not trivial, requiring changes across the entire ecosystem — from EDA software to mask-making tools and handling systems. ASML, the Dutch lithography equipment supplier, is working with TSMC on the transition, backed by support from Intel and Samsung.

"We expect the adoption of High NA EUV to increase progressively along the device scaling roadmap, first using current 6-inch masks and then further supported by 12-inch masks, which enable greater scanning," ASML said.

When used with conventional 6×6-inch photomasks, High-NA EUV scanners have only half the exposure field of their Low-NA counterparts. This creates challenges for manufacturing very large dies, such as AI accelerators, forcing chipmakers to either stitch multiple exposure fields together or adopt multi-chiplet designs — approaches that bring their own trade-offs in productivity and power consumption.

Why This Matters

TSMC's adoption of High-NA EUV will determine the pace of semiconductor scaling beyond 2nm-class nodes, directly affecting the performance and cost of future chips for smartphones, AI accelerators, and data centers.
The transition to larger photomasks could reshape the economics of chip manufacturing, enabling larger monolithic dies and reducing the need for complex multi-chiplet designs.
TSMC's timeline — years behind Intel's announced High-NA EUV deployment — highlights the divergent strategies of the two leading foundries and may influence customer decisions.

Background

High-NA EUV lithography uses a 0.55 numerical aperture lens, compared to 0.33 in current Low-NA EUV systems, enabling finer patterning. ASML is the sole supplier of these systems, which cost around $400 million each. TSMC has long been cautious about adopting High-NA, arguing that its existing Low-NA tools could be extended through multi-patterning and other techniques. The company's new roadmap suggests it now sees High-NA as necessary for the most advanced nodes, particularly as transistor architectures evolve from FinFET to gate-all-around (GAA) and eventually complementary field-effect transistors (CFETs).

Key Perspectives

TSMC: The company aims to start High-NA EUV production in 2030 with conventional masks, then transition to larger masks by 2033. This allows it to amortize existing investments and solve exposure field limitations gradually. Intel: Intel has been more aggressive, ordering ASML's first High-NA systems and planning to use them for its 18A node (roughly equivalent to 1.8nm). Intel's earlier adoption could give it a process advantage, but the risk of lower yields and higher costs is higher. Industry ecosystem (EDA, mask makers): The shift to 6×12-inch photomasks requires a complete overhaul of design tools, mask manufacturing, and handling equipment. This will take years and requires coordination across the entire supply chain.

What to Watch

Specific node announcements: Whether TSMC formally designates A10 or A11 as the first High-NA EUV node, and the expected timeline for tape-outs.
Intel's High-NA EUV ramp: If Intel successfully achieves volume production before 2030, it could shift the competitive dynamics in foundry services.
ASML's delivery schedule: Any delays in High-NA EUV tool deliveries or the larger photomask infrastructure would push back the entire industry timeline.

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