China advances chipmaking without EUV, at a rising cost

Multiple patterning lets SMIC approach 5nm-class density, but defects, yields and economics still trail the West

By LineZotpaper

Published23 October 2026

Read Time3 min

China's chipmakers are producing increasingly advanced processors without access to ASML's extreme ultraviolet (EUV) lithography machines, but the techniques they rely on carry a growing price in defects, larger dies and poorer yields, according to industry experts and analysts.

Export controls have kept ASML's EUV machines, which use 13.5nm-wavelength light to print the most intricate processor features, out of China. In their place, Chinese manufacturers have pushed older deep ultraviolet (DUV) tools harder, dividing complex chip layers into simpler patterns and exposing them multiple times, a technique known as multiple patterning.

The approach has carried China further than many expected. Teardowns of Huawei's Mate 60 Pro in 2023 found its Kirin 9000S processor had been made by SMIC using a second-generation 7nm-class process without EUV. Analysis of the later Kirin 9030 found SMIC's DUV-based process closer still to the density associated with 5nm manufacturing, though still behind the leading processes of TSMC and Samsung.

The trade-offs are significant, said Chris Mack, co-founder and CTO of semiconductor firm Fractilia. Industry conventional wisdom put three exposures on a 193-nanometer immersion tool at roughly the same cost as one EUV exposure; beyond that, EUV wins on cost. Each additional exposure also multiplies opportunities for misalignment and defects, he said.

Chip designers can leave extra space around features to make manufacturing reliable, but that enlarges the die, reducing how many chips fit on a wafer. "You don't sell wafers, you sell die," Mack said. "The question is: how many die can I fit onto that wafer, and how many of those die yield, and therefore how many chips can I sell per wafer?"

The efficiency gap shows up in memory. Morgan Stanley estimated in June that Chinese DRAM maker CXMT produced only around one-third as many bits per wafer as Western rivals, calling access to lithography a "hard ceiling" on Chinese memory development. Douglas Fuller, a researcher at Copenhagen Business School, said innovations to engineer around EUV for advanced logic chips were unlikely to be "very efficient and effective."

Mack cautioned that node labels such as "7nm" and "5nm" "almost have no meaning" without reference to actual measurements. SMIC's N+3 process represents progress towards 5nm-class manufacturing, he said, but remains significantly less scaled than the established 5nm processes from Samsung and TSMC.

Micron shows how far DUV can be stretched in memory: its 1-alpha DRAM generation was developed without EUV and proved competitive. "They pushed 193 farther than any of the other memory makers did," Mack said. But "memory is a lot easier than logic," and Micron's newer 1-gamma process uses EUV, which the company says delivers more than 30% greater bit density per wafer than its predecessor.

Mack doubts a three-nanometer or two-nanometer node will be economically viable without EUV. Chinese makers can keep pushing DUV while accepting larger dies, poorer yields and longer manufacturing times, or they can throw capacity and money at the problem. Morgan Stanley expects CXMT's global DRAM share to grow from 14% in 2026 to 16% in 2028 purely through new greenfield capacity, and projects China's AI chip self-sufficiency rising from 42% in 2025 to 70% by 2030.

Analysis

Why This Matters

China's progress in making advanced chips without EUV challenges the assumption that export controls would act as a hard choke point, and will feed the debate over whether the policy is working.
The cost and efficiency gaps matter for global competition: Chinese chips are likely to be larger, yield fewer working processors per wafer and cost more to make, shaping prices and product competitiveness wherever Chinese supply is used.
Morgan Stanley projects China's AI chip self-sufficiency will rise from 42% in 2025 to 70% by 2030, a shift with direct implications for AI supply chains and future export policy.

Background

EUV lithography, which uses 13.5nm-wavelength light, is the industry's most advanced chip-printing technology and is made exclusively by Dutch firm ASML. Export controls block its sale to China, leaving Chinese manufacturers to work with older 193nm immersion DUV tools. The technique of multiple patterning splits a complex layer into several simpler patterns exposed in sequence, but each extra exposure adds time, cost and defect risk. Memory devices have proven easier to adapt than the far more complex logic processors found in phones and computers.

Key Perspectives

Chinese chipmakers (SMIC and CXMT): making real progress without EUV: SMIC has produced 7nm-class chips and is approaching 5nm-class density, while CXMT plans a move to 1-alpha DRAM for HBM3e. Their answer to the cost gap is to accept the trade-offs and build more capacity.

Lithography experts (Chris Mack): multiple patterning works only up to a point. Beyond roughly three or four pattern layers, EUV becomes the cheaper route, and a 3nm or 2nm node is unlikely to be economically viable without EUV.

Analysts and researchers (Morgan Stanley and Douglas Fuller): lithography access remains a "hard ceiling" for Chinese memory, and the bits-per-wafer gap is real. But alternative levers, including advanced packaging, could let DUV carry the latest DRAM generations by the end of the decade, and Micron's 1-alpha experience shows how far DUV can stretch in memory.

What to Watch

SMIC's next DUV-based process generations, and whether measured density and yields begin to close the gap with TSMC and Samsung.
CXMT's 1-alpha DRAM ramp and its push into HBM3e, an application that has driven other memory makers toward EUV.
China's DRAM share and AI chip self-sufficiency against Morgan Stanley's forecasts: DRAM supply rising from 14% in 2026 to 16% in 2028, and AI chip self-sufficiency reaching 70% by 2030.

Sources

China can make advanced chips without EUV, but the bill keeps growing · Latest from Tom's Hardware

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12 claims in this story checked against 1 source: 9 supported.

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SupportedChina is advancing chipmaking without EUV at a rising cost.Latest from Tom's Hardware: “However, as multiple patterns are applied there are more chances for defects, longer manufacturing times, and higher bills.”
Partly supportedMultiple patterning lets SMIC approach 5nm-class density, while defects, yields and economics still trail the West.Latest from Tom's Hardware: “More recently, analysis of Huawei’s Kirin 9030 found SMIC had pushed its DUV-based process closer still to the density associated with 5nm manufacturing – although it continued to lag behind the leading processes used by TSMC and Samsung.”
SupportedChinese chipmakers are producing increasingly advanced processors without EUV, but their techniques bring more defects, larger dies and poorer yields.Latest from Tom's Hardware: “They can keep pushing DUV while accepting larger dies, poorer yields, longer manufacturing times – or some combination of all three.”
SupportedExport controls have kept ASML EUV machines out of China; the machines use 13.5nm-wavelength light.Latest from Tom's Hardware: “The machines, made exclusively by Dutch manufacturer ASML, use 13.5nm-wavelength light to print some of the most intricate features found on modern processors. Sales of ASML’s EUV systems are subject to export restrictions”
SupportedChinese manufacturers use multiple patterning, exposing complex chip layers multiple times with older DUV tools.Latest from Tom's Hardware: “Rather than trying to print an overly intricate chip layer in a single pass, Chinese manufacturers are dividing up the complex design into several simpler patterns.”
SupportedTeardowns found Huawei’s 2023 Mate 60 Pro used an SMIC-made Kirin 9000S on a second-generation 7nm-class process without EUV.Latest from Tom's Hardware: “Teardowns of Huawei’s Mate 60 Pro in 2023 found the phone’s Kirin 9000S processor had been made by SMIC using a second-generation 7nm-class manufacturing process without EUV.”
SupportedThree exposures on a 193-nanometer immersion tool cost about as much as one EUV exposure, and EUV becomes more cost-effective beyond that.Latest from Tom's Hardware: ““When this transition first began, what everyone in the industry said as conventional wisdom is that cost-wise, three exposures on a 193 immersion tool cost about the same as one exposure on an EUV tool,” Mack said in an interview with Tom’s Hardware Premium.”
Partly supportedEach additional exposure multiplies opportunities for misalignment and defects.Latest from Tom's Hardware: “The more individual exposures needed to produce a single layer, the more opportunities there are for things to go wrong.”
SupportedMack said, “You don't sell wafers, you sell die,” and asked how many die fit on a wafer and yield.Latest from Tom's Hardware: ““You don't sell wafers, you sell die,” Mack said. “The question is: how many die can I fit onto that wafer, and how many of those die yield, and therefore how many chips can I sell per wafer?””
SupportedMorgan Stanley estimated that CXMT produced around one-third as many bits per wafer as Western rivals and called access to lithography a “hard ceiling” on Chinese memory development.Latest from Tom's Hardware: “In a June report, Morgan Stanley estimated that Chinese DRAM manufacturer CXMT was producing only around one-third as many bits per wafer as Western competitors. The analysts believed the older process node only accounted for around a third of that shortfall, but said access to lithography was a “hard ceiling” on Chinese memory development.”
Partly supportedMorgan Stanley expects CXMT’s global DRAM share to rise from 14% in 2026 to 16% in 2028 purely through new greenfield capacity.Latest from Tom's Hardware: “Morgan Stanley assumes CXMT remains stuck on its 1-alpha process without EUV, yet still increases its share of global DRAM bit supply from 14% in 2026 to 16% in 2028 simply by building more greenfield capacity.”
SupportedMorgan Stanley projects China’s AI chip self-sufficiency will rise from 42% in 2025 to 70% by 2030.Latest from Tom's Hardware: “The bank also expects China’s AI chip self-sufficiency to rise from 42% in 2025 to 70% by 2030 through new advanced-node capacity, improving yields and heavy state support”