Micron abandons 4F² DRAM after decades of research, calls density claims a 'myth'

Memory maker will stick with conventional 6F² cells and pursue 3D DRAM instead, diverging from Samsung and SK hynix

By LineZotpaper
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Micron has ended its two-decade pursuit of 4F² DRAM memory cells, concluding the architecture offers no meaningful density advantage and introduces unsustainable complexity and cost. The company will instead continue scaling conventional 6F² planar DRAM and eventually transition to 3D DRAM, a move that puts it on a different path from rivals Samsung and SK hynix, which still list 4F² cells on their roadmaps.

The decision was disclosed by Scott DeBoer, president and chief technology and products officer at Micron, during a company event on Wednesday. He described the widely held belief that 4F² cells automatically boost density as a "bit of a myth," emphasizing that capacitor pitch, not transistor footprint, is the real determinant of DRAM bit density.

4F² memory cells have long been a target for the DRAM industry because their nominal cell area is about 33% smaller than conventional 6F² designs. In theory, that could increase the number of memory cells per wafer by up to 50%, lowering cost per bit. But in practice, DeBoer said, the transistor must still fit beneath the capacitor, whose physical dimensions ultimately govern cell size.

"It is important to understand the capacitor pitch, the capacitor size, and dimensions, is what sets the DRAM bit density, not whether it is 6F², 4F², 8F²," DeBoer said. "You can build the cells, the transistors underlying them in different ways, but they still have to fit under the capacitor pitch, which sets the DRAM [cell size]."

Micron acknowledged it has built experimental 4F² devices and that earlier nodes could have supported the architecture. But for future nodes, the company sees no viable scaling path. DeBoer noted fundamental physics limitations that make 4F² unsustainable at smaller dimensions, saying the architecture would ultimately require a jump to 3D DRAM anyway.

Instead of adopting 4F², Micron plans to extend conventional 6F² planar DRAM for the next several generations. Advanced lithography, new materials, and wafer bonding will be used to shrink the capacitor pitch and improve bit density. The company's upcoming 1δ process, scheduled for volume production in the second half of 2027, promises a mid-20% improvement in density over its predecessor. Micron also intends to adopt high-NA EUV lithography for future DRAM.

The long-term plan is 3D DRAM, which stacks memory cells vertically. Micron is already developing multiple generations of 3D DRAM production nodes but has not announced when they will enter commercial production. DeBoer said the company will transition when the new architecture offers the right balance of density, complexity, and cost.

Industry analysts at TechInsights report that both Samsung and SK hynix still have 4F² memory cells in their roadmaps. Micron's rejection of the technology follows a similar pattern to its earlier decision to delay adoption of EUV lithography, a move that still allowed it to remain cost- and performance-competitive with rivals.

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Analysis

Why This Matters

  • Micron's decision could reshape DRAM manufacturing roadmaps if the 4F² cell turns out to be a dead end for the industry as a whole.
  • If Samsung and SK hynix proceed with 4F² and encounter the same scaling limits Micron describes, it could lead to higher costs or delayed node introductions for those companies.
  • The shift reinforces the importance of capacitor pitch and 3D stacking as the primary levers for continued DRAM density improvements, directly affecting future memory prices and device capabilities.

Background

DRAM memory cells are described by a figure of merit equal to the square of the minimum lithographic feature size (F). For decades the standard cell has been 6F², but a 4F² cell would reduce area by about one-third, offering a path to higher density without shrinking features as aggressively. Researchers have pursued 4F² since the early 2000s, with several manufacturers demonstrating test chips. Micron itself claimed to have invented the 4F² cell. The company's rethink now challenges a longstanding industry assumption.

Key Perspectives

Micron: After two decades of evaluation, the company concludes that 4F² adds manufacturing complexity and cost without delivering real density benefits because capacitor pitch, not transistor area, limits cell size. Scaling 4F² beyond current nodes runs into fundamental physical barriers, making 3D DRAM the only sustainable path. Samsung and SK hynix: The two largest DR makers have not pulled back from 4F² roadmaps, suggesting they see a near-term competitive advantage in the architecture or believe they can overcome the scaling challenges Micron cites. Industry skeptics: Some engineers and analysts may question whether any manufactuer can make 4F² work economically at advanced nodes, or whether the real answer lies in alternative paths such as stacked capacitors or vertical transistors.

What to Watch

  • Whether Samsung or SK hynix demonstrate working 4F² DRAM at a density that matches or exceeds Micron's upcoming 1δ process.
  • Micron's disclosed timeline and density targets for its first 3D DRAM product.
  • Any adjustments to equipment orders for EUV or high-NA EUV as Micron and its rivals calibrate their process tooling.

Sources

Checked

12 claims in this story checked against 1 source: 9 supported.

Show each claim
  1. Partly supportedMicron ended a two-decade pursuit of 4F² DRAM.Latest from Tom's Hardware: “The path with 4F² DRAM is always been an option through time, and we have evaluated it and not pursued it due to increased complexity and cost through this past two-decade period of time.”
  2. Partly supportedMicron calls the claim that 4F² boosts density a “myth.”Latest from Tom's Hardware: “From our investigation of this technology over the past couple of decades, it is a bit of a myth that 4F² actually provides anything versus 6F².”
  3. SupportedMicron plans to keep scaling conventional 6F² DRAM and eventually move to 3D DRAM.Latest from Tom's Hardware: “Instead of adopting the 4F² DRAM cell architecture, Micron plans to continue scaling conventional 6F² DRAM.”
  4. Partly supportedSamsung and SK hynix still have 4F² cells on their roadmaps, according to industry analysts at TechInsights.Latest from Tom's Hardware: “Interestingly, both Samsung and SK hynix still have 4F² memory cells in their roadmaps (according to TechInsights)”
  5. SupportedMicron says 4F² offers no meaningful density advantage and adds complexity and cost.Latest from Tom's Hardware: “Micron has concluded that the architecture offers no meaningful density advantages, increases manufacturing complexity and costs, and has fundamental scaling limitations.”
  6. SupportedDeBoer said: “It is important to understand the capacitor pitch, the capacitor size, and dimensions, is what sets the DRAM bit density, not whether it is 6F², 4F², 8F²,”Latest from Tom's Hardware: “It is important to understand the capacitor pitch, the capacitor size, and dimensions, is what sets the DRAM bit density, not whether it is 6F², 4F², 8F²,”
  7. SupportedDeBoer said: “You can build the cells, the transistors underlying them in different ways, but they still have to fit under the capacitor pitch, which sets the DRAM [cell size].”Latest from Tom's Hardware: “You can build the cells, the transistors underlying them in different ways, but they still have to fit under the capacitor pitch, which sets the DRAM [cell size].”
  8. SupportedA 4F² cell is about 33% smaller in area than a conventional 6F² cell.Latest from Tom's Hardware: “At identical feature dimensions, a 4F² cell occupies approximately 33% less area than a 6F² cell”
  9. SupportedIn theory, 4F² could increase the number of memory cells per wafer by 50%.Latest from Tom's Hardware: “which could theoretically increase the number of memory cells per wafer by 50%.”
  10. SupportedMicron has manufactured experimental 4F² devices.Latest from Tom's Hardware: “DeBoer fully acknowledges that 4F² DRAM is technically feasible and that Micron itself has manufactured experimental devices based on the architecture.”
  11. SupportedMicron’s upcoming 1δ process is scheduled to enter volume production in the second half of 2027.Latest from Tom's Hardware: “its upcoming 1δ process technology, scheduled to enter volume production in the second half of 2027”
  12. SupportedThe 1δ process promises a mid-20% improvement in bit density over its predecessor.Latest from Tom's Hardware: “promises a mid-20% improvement in bit density compared with its predecessor.”

Zotpaper

Written by Harper Lane on the Tech & AI desk. Claims checked by Ines Fairley, verification. Edited by Angus Burke, chief sub. Plate by Ollie Flash, picture desk.

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