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SK hynix develops tiny custom CPU cores for SSD controllers to offload Arm processors

Company plans H-TPU across NAND portfolio as PCIe speeds outpace general-purpose core scaling

By LineZotpaper
Published
Read Time2 min
SK hynix has detailed plans to reduce reliance on power-hungry CPU cores in its SSD controllers with an in-house designed core called the Hynix Transaction Processing Unit (H-TPU). The tiny, programmable cores handle repetitive I/O tasks with dramatically lower power and area consumption, leaving management functions to a traditional Arm CPU. The company aims to apply H-TPU across its NAND product line, beginning with next-generation enterprise SSD controllers.

SK hynix outlined the H-TPU architecture at the International SoC Design Conference (ISOCC 2026) earlier this week. Vice President of system-on-chip design Koo In-jae said that SSD controller CPUs have reached their limits on power and area. PCIe bandwidth doubles every generation, he noted, and controller CPU clocks and control capability cannot keep pace.

The H-TPU is a small core with a four-stage, in-order pipeline. It is not superscalar and does not use out-of-order execution. It is designed for specific tasks: read and write command processing, metadata management, and buffer control. Each H-TPU draws about 2.5% of the power of a general-purpose CPU core and occupies roughly 4% of its area.

SK hynix broke more than 100 detailed storage control functions across “dozens of small TPU clusters,” according to reports from ZDNet Korea. The total number of H-TPUs exceeds 100, though the number of cores per cluster has not been disclosed. The main Arm CPU still handles error recovery, exception handling, and storage policy management.

The design is a response to the scaling challenge evident in competitor products. Marvell’s PCIe 6.0 Bravera SC6 controller uses 12 Cortex-R82 cores in two clusters plus three Cortex-M7 cores and a secure Cortex-M3, up from 10 Cortex-R8 and Cortex-M7 cores in its PCIe 5.0 predecessor.

SK hynix plans to apply H-TPU across its NAND products, including enterprise SSD controllers, where demand for high IOPS is most pressing. The cores come with a dedicated compiler and development tools for specialized code.

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Analysis

Why This Matters

  • SSD controllers are struggling to keep up with increasing PCIe speeds without consuming excessive power and silicon area. SK hynix's approach could set a new efficiency benchmark for enterprise storage.
  • By offloading repetitive I/O tasks to tiny custom cores, the main CPU can focus on management and exception handling, potentially improving overall drive performance and reducing power draw.
  • The shift from general-purpose cores to specialized processing units in storage controllers reflects a broader industry trend toward heterogeneous computing in system-on-chip designs.

Background

SSD controller design has become increasingly complex as PCIe generations advance. Each leap in bandwidth demands more processing power to manage the I/O path. Traditional approaches have added more general-purpose CPU cores, but this scales poorly in terms of power and die area. SK hynix's H-TPU aims to break that pattern by using many small, programmable cores that each handle a narrow set of functions, leaving overall management to a conventional Arm core. The company has not disclosed a timeline for products incorporating H-TPU, but the target is next-generation enterprise SSDs.

Key Perspectives

SK hynix: The H-TPU enables efficient scaling of SSD controller processing without large power and area penalties. The design allows idle cores to drop into minimum-power mode, and the dedicated compiler enables custom optimization. Competitors (Marvell, Phison, Silicon Motion): Current controllers rely on increasing numbers of Arm cores to meet performance demands. SK hynix's approach could force a rethink if it delivers significant efficiency gains. Storage industry observers: Success will depend on how well the H-TPU toolchain works for firmware developers, and whether the performance of many small, in-order cores matches that of fewer, larger out-of-order cores in real-world workloads.

What to Watch

  • First product announcements from SK hynix incorporating H-TPU, expected in next-generation enterprise SSD controllers.
  • Performance and power benchmarks comparing H-TPU-based controllers against Marvell's 12-core Bravera SC6.
  • Adoption by other NAND manufacturers and whether the H-TPU architecture influences future controller designs across the industry.

Sources

Zotpaper

Written by software from the reporting listed above, scored by an automated standards desk, and published without a person reading it first. If something here is wrong, tell the editor and it will be put right.

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