AMD's Venice Epyc processors mark the company's biggest architectural shift in CPU design since Rome debuted in 2019, according to details the chipmaker released in a whitepaper late last week. The document, which The Register says is clearly aimed at pushing back on Nvidia's marketing around its Vera CPUs, offers the fullest picture yet of AMD's Zen 6-based lineup — described as its broadest CPU portfolio ever, spanning general purpose, HPC, AI and eventually consumer platforms.
The stack breaks into four buckets: high-performance, enterprise, HPC and AI. The performance-optimized parts, built on the Epyc 9006 SP7 platform, are the ones that will actually ship in 2026; pretty much everything else rolls out over the course of 2027.
Headline specs for the SP7 platform include up to 256 cores, 16 channels of DDR5, and 128 lanes of CXL 3.1-compatible PCIe 6.0 connectivity. As with last year's Turin parts, Venice comes in two flavors: density-optimized and frequency-optimized. The 256-core version is the density-optimized part, alongside a 96-core chip capable of boosting to 5 GHz.
Peeling back the heat spreader, both chips feature a pair of I/O dies surrounded by eight core-complex dies (CCDs) — twice the I/O but half as much compute silicon as Turin, yet with higher core counts. AMD has doubled the compute cores per chiplet to 32 and quadrupled shared L3 from 32 MB to 128 MB per chiplet, meaning fully loaded Venice CPUs now carry a gigabyte of L3 onboard. The frequency-optimized parts are more conservative, with 12 cores and 48 MB of L3 per chiplet, up about 50 percent over last gen.
Arguably the more interesting change is the cache hierarchy: there is now no difference between a Zen 6C core and a Zen 6 core aside from clock speeds. In prior generations, AMD's compact ZenC CCDs shared the same 32 MB pool of L3 as standard Zen CCDs, leaving top-spec parts with half as much L3 per core. With Venice, every CCD gets at least 4 MB of shared L3 per core. The Register notes AMD's compact Zen cores are not equivalent to Intel's efficiency cores — Intel uses completely different microarchitectures for its P and E cores, while AMD simply trades clock speed for a more compact form factor with an identical ISA.
The move to two I/O dies is another change, possibly tied to the interconnect used to connect the CCDs to the I/O subsystem, with the dies butted up against each other this time. The I/O itself is largely unchanged at 128 lanes.