Researchers demonstrate method to control 2D semiconductor crystal growth for future chips

Technique achieves 99.3 per cent yield of single crystals on test substrate, targeting commercial use around 2030

By LineZotpaper

Published11 October 2026

Read Time2 min

Researchers have demonstrated a way to control where two-dimensional semiconductor crystals begin growing on a wafer, potentially removing a key barrier to manufacturing next-generation transistors at scale. The technique, described in a paper published in Nature on October 7, uses an etching flux to suppress random nucleation and force a single crystal to form at the centre of each patterned region. The team behind the work includes researchers from KAIST in South Korea and the startup TDS Innovation.

Two-dimensional materials are atomically thin layers, such as graphene (a single layer of carbon atoms), but graphene lacks a band gap, making it unsuitable for conventional switching transistors. Monolayers of transition-metal dichalcogenides (TMDs) such as molybdenum disulfide (MoS₂) do have a band gap and are being studied for future transistors and nanoscale devices.

A longstanding problem is that when these 2D semiconductors are grown on a wafer, crystals start forming at random points, leading to multiple crystals in each region. When these crystals meet, grain boundaries form that degrade electrical performance and device uniformity. The new approach, called etching-flux-mediated single-centred nucleation (EF-SCN), uses oxygen released from an oxide barrier to create a lateral etching flux that suppresses nucleation everywhere except at the geometric centre of each patterned area.

The researchers built working field-effect transistors (FETs) using the process and reported higher charge-carrier mobility than previously achieved for selectively grown MoS₂ transistors. In a test across a two-centimetre substrate, single crystals appeared at 397 of 400 patterned sites, a yield of 99.3 per cent.

Co-author Kibum Kang, who is also co-CEO of TDS Innovation, said the ability to control where crystal growth begins could allow high-quality 2D single crystals to be formed uniformly and developed into a next-generation process that brings logic and memory closer together. Jony Jung of TDS Innovation told The Register the company aims to enable commercial use of 2D semiconductors around 2030. He added that accelerating demand from artificial intelligence, including physical AI and robotics, could help bring adoption forward, though production timing would depend on further validation.

Two-dimensional semiconductors are also being investigated for complementary field-effect transistors (CFETs), which stack n-type and p-type transistors vertically, a 3D stacking approach that has been demonstrated by IBM and Intel.

Analysis

Why This Matters

If the technique scales, it could enable denser, more energy-efficient chips by stacking 2D logic and memory vertically, reducing data movement.
The 99.3 per cent yield on a small substrate suggests the method is promising for manufacturing, but it is not yet a commercial process.
The timeline (around 2030) aligns with industry roadmaps for beyond-silicon transistors, though validation at wafer scale lies ahead.

Background

Two-dimensional semiconductors like MoS₂ are atomically thin materials with a band gap, making them candidates for transistors beyond the limits of silicon. A major obstacle has been uncontrolled nucleation during growth, leading to grain boundaries that hurt performance. This work addresses that by using an etching flux to force single-crystal growth at defined locations. The approach is still at the research stage and has only been demonstrated on a two-centimetre substrate, far from the 300-millimetre wafers used in modern fabrication.

Key Perspectives

Researchers and TDS Innovation: The technique offers a path to uniform single crystals, which could be integrated with silicon chips for 3D stacking of logic and memory. They see demand from AI as a potential accelerant.

Industry sceptics: Production at commercial scale is unproven; the substrate tested is much smaller than production wafers, and further validation of electrical performance and reliability is needed before foundries adopt the process.

Chipmakers and foundries: Companies such as Intel and IBM are exploring 3D transistor designs (CFETs) and may be interested in 2D materials, but will require demonstrated compatibility with existing fabrication processes.

What to Watch

Progress in scaling the technique to larger wafer sizes (e.g., 300 mm) and maintaining yield.
Further validation of transistor performance, including uniformity across a full wafer.
Announcements from TDS Innovation or partners about pilot production lines or foundry collaborations toward 2030.

Sources

Researchers work out how to control 2D semiconductor growth for future chips — www.theregister.com - Articles