CXMT's first 4F² product will be a server DDR5 RDIMM built on a denser cell layout that uses vertical transistors to shrink the cell's footprint by about one-third on paper, according to president Cao Kanyu. No speeds or capacities for the new memory have been announced.
A 4F² cell is 2F by 2F, roughly two-thirds the area of current 6F² cells at the same feature size, and designs so far all stand the transistor up. CXMT's version, which it calls the Vertical Surrounded Gate (VSG) transistor, has a channel that stands vertically with the gate wrapped around it, allowing stronger gate control with less leakage. The company has published research and patent filings on the technology, with papers in 2021, 2023 and 2025, and demonstrated an 8Gb full-array research example at IEDM 2023. Cao added that CXMT now holds more than 300 published patent families tied to 4F².
The industry broadly is moving toward 4F² with 3D solutions that decouple DRAM and CMOS processes and combine them with wafer-level hybrid bonding, allowing logic and cell density to be optimized independently. Cao also discussed CXMT's own hybrid-bonding work, which began in 2019 and has published patents.
The announcement comes as CXMT strengthens its market position. Its fifth-generation G5 DRAM technology platform, announced September 20, is in mass production. TrendForce puts CXMT's share of global DRAM revenue at 9.5% in the second quarter, up from 7.6% in the first, good for fourth place. Last November the company showed off DDR5-8000 and LPDDR5X-10667 memory, signalling it is a manufacturer to be taken seriously by the biggest existing players.
Rivals are pursuing the same direction. Samsung presented a 16Gb, 10nm-class 4F² DRAM design in its ISSCC 2026 paper in February, using vertical-channel transistors with the array bonded on top of the periphery via wafer-to-wafer hybrid copper bonding, a technique the company says raises dies per wafer by more than 20% with the same design rules. In April, The Elec reported that Samsung had a working 4F² VCT die on its sub-10nm "10a" process, with mass production targeted for 2028, though later South Korean reports clouded that date, splitting the VCT version off as "D0a-V" with no firm timeline. SK hynix laid out plans at VLSI 2025 for a 4F² vertical-gate platform.