Arm unveils Neoverse CSS N4 'Ranger' platform with up to 128 cores on TSMC N3P

Arm's new Neoverse CSS N4 platform represents the latest iteration of its Compute Subsystem (CSS) program, which allows customers to design semi-custom chips using Arm's verified building blocks. The N4 platform supports between 8 and 128 Neoverse N4 cores, running at up to 3.8 GHz, with clock speeds likely dropping as core count increases.

The platform features up to 256 MB of L3 cache per die, with 2 MB of L2 cache per core, and 64 KB each of L1 instruction and data cache. For memory, it supports either DDR5 or LPDDR6, and I/O includes up to 128 lanes of PCIe 7/6 and CXL 4.0. Multi-chiplet and multi-socket designs are supported via UCIe chip-to-chip interconnects.

Compared to the Neoverse CSS N2 platform, which topped out at 64 cores, 1 MB of L2 cache per core, and 64 MB of L3 cache with DDR5 or LPDDR5 and 64 PCIe 5.0/CXL lanes, the N4 represents a significant leap. Arm claims the N4 delivers twice the socket performance of Neoverse N3, 1.25x performance per watt, and 1.75x memory bandwidth when configured with 128 cores at 3 GHz and 2 MB L2 cache per core.

The N-series cores are optimized for performance per watt, generally used in less-demanding cloud workloads and accelerators, as opposed to Arm's V-series cores which target maximum performance. Examples of N-series deployments include Intel's IPU Adapter E2100 (Neoverse N1) and Microsoft's Azure Cobalt 100 (Neoverse N2). The N4 cores are codenamed Dionysus, and a V4 counterpart (codenamed Vega) is expected on Arm's 2024 roadmap.

Arm has not yet announced any partners for the CSS N4 platform, but the company typically requires only a few large contracts for its CSS program. Actual products using Neoverse N4 cores are not expected to appear in the market for some time.

Why This Matters

Arm's CSS N4 platform offers a significant performance and efficiency upgrade for cloud infrastructure, potentially accelerating adoption of Arm-based servers in data centers.
The platform's support for up to 128 cores per die and advanced I/O (PCIe 7/6, CXL 4.0) positions it to handle demanding workloads like AI inferencing, networking, and data processing.
The move to TSMC N3P process node could yield power and density advantages over competing x86 and RISC-V designs.

Background

Arm's Neoverse CSS program allows cloud providers and chip designers to create custom silicon using Arm's pre-validated core blocks, reducing time-to-market and development risk. The N-series is designed for performance-per-watt efficiency, making it suitable for infrastructure CPUs, accelerators, and smart NICs. Previous N-series chips have been used by Microsoft (Azure Cobalt 100) and Intel (IPU). The new N4 platform builds on the successful N2, with major improvements in core count, cache, and memory bandwidth.

Key Perspectives

Cloud providers (AWS, Azure, Google Cloud): They can leverage the CSS N4 to build custom server chips that balance performance and power, potentially reducing dependence on x86 vendors and enabling differentiated offerings. Chip designers (Nvidia, Intel, others): Arm's CSS lowers the barrier to designing high-performance server chips, but they must compete with Arm's own V-series and custom cores, as well as x86 and RISC-V alternatives. Critics/Skeptics: The N-series is not intended for high-performance computing; it may struggle against V-series or x86 in raw throughput. Also, adoption depends on software ecosystem maturity and partner commitment.

What to Watch

Announcement of first CSS N4 partners: A major cloud provider like AWS, Azure, or Google Cloud would signal strong market validation.
Performance benchmarks from Arm or partners: Real-world throughput and power efficiency numbers will determine competitiveness.
Release timeline for the Neoverse V4 (Vega): The V-series could offer a higher-performance option for compute-intensive workloads.

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