Former Intel CEO Pat Gelsinger backs Nagare Labs to break the memory wall

Former Intel chief executive Pat Gelsinger is backing Nagare Labs, a memory startup founded by Georgia Tech researchers that says it has a path past the memory wall with a new type of memory built on oxide semiconductors.

Gelsinger, now a partner at the venture firm Playground Global, told The Register that the industry has seen no major forms of memory innovation in three decades, with SRAM, DRAM and flash the only memory types in broad deployment. Nagare's Z2RAM, he said, combines the best characteristics of DRAM, SRAM and flash into a device that is dense like DRAM, fast like SRAM and scalable like flash, while avoiding what he called the limits of high-bandwidth memory in power, density and shoreline bandwidth. With AI a memory-limited workload, he said, the explosion of AI demand has created extraordinary interest and capital for a breakthrough.

The startup was founded by Georgia Institute of Technology researchers Suman Datta and Shimeng Yu, building on years of work on ferroelectrics and resistive RAM. Instead of DRAM's one-transistor, one-capacitor cell, Z2RAM uses two transistors and stores charge in the gate capacitance of the second transistor. Datta said the cell will rival SRAM in speed while functioning more like DRAM, and because reading it is non-destructive, it avoids DRAM's write-back penalty. The technology is designed to be integrated directly onto compute logic using 3D hybrid bonding, in a role similar to AMD's 3D V-Cache.

Nagare also plans to stack cells vertically in a way Datta likened to NAND, which he argued should make the technology cheaper and easier to manufacture than HBM or LPDDR. In its first incarnation, Z2RAM promises bit density more than five times that of SRAM: a 64MB SRAM tile could become 320MB at comparable bandwidth. The Register reports that could cut by five times or more the number of chips needed for SRAM-heavy accelerators serving frontier AI models.

Nagare has raised $5 million in seed funding. “Where we are is literally lab prototypes,” Datta told The Register. The company is looking for an R&D fab partner to scale beyond a university clean room, with a goal of sampling working Z2RAM tiles within four years and starting production shipments within a decade. Datta said Nagare is also open to working directly with chipmakers to integrate Z2RAM into designs, similar to how AMD worked with TSMC on its 3D V-Cache tiles.

Significant hurdles remain. “There's no standard that we have right now to integrate this new memory with the accelerator,” Yu told The Register. To get the benefits of high-capacity, high-speed memory, he said, the technology relies on 3D bonding, and there is no standardization for it, which may force Nagare to design an interface itself. Datta acknowledged oxide semiconductors are prone to atomic vacancies, where even a few electrons can shift a transistor's threshold voltage and upset a cell, so much work is going into reliability. He also noted that many memory startups have failed because systems impose stringent standards, but argued that changing dynamics and new protocols have opened the door to adventurous memory designs again.