Micron roadmap includes 3D DRAM and custom AI memory

Micron’s president and chief technology and products officer, Scott DeBoer, said at the company’s event earlier this month that DRAM is nearing atomic limits. While Micron has confidence in several more planar nodes, he said, the company is very focused on introducing 3D DRAM at the optimal time from a cost and performance point of view.

The current 1γ node, Micron’s first to use EUV lithography, is in high-volume manufacturing. The 1δ process, now in the yield ramp stage, is expected to increase bit density by mid-20 percent compared with 1γ, and Micron plans to manufacture it in the U.S. for next-generation DDR, LPDDR, graphics memory, HBM5, vertical HBM and vertical Edge Inference Memory (vEIM) products.

Micron cited a lack of a viable scaling path beyond where it is today; CXMT, Samsung and SK hynix, by contrast, plan to produce DRAM with 4F² cells. Its planar roadmap continues with 1ε, which will rely on wafer bonding and has no announced production schedule; ζÅ, which will introduce High-NA EUV lithography to memory manufacturing and will not be in production until at least 2030, later than the 2028 adoption Samsung and SK hynix have planned; and ηÅ, the most distant generation, still in pathfinding. Two generations of 3D DRAM, called 3D1 and 3D2, are under development, with architectures, layer counts and density targets not yet disclosed.

Starting with HBM4E, Micron will offer both standard and custom HBM products, followed by custom HBM5E, vertical HBM and vEIM, marking the re-emergence of custom memory in mass-produced products. DeBoer said that when Micron co-designs a base die, certain logic elements are “generally an offload from GPU circuitry anyway onto the base die to put it closer to the memory,” and that “moving what makes more sense onto the base die will still be a reality in [the] vertical HBM timeframe as well.” Vertical HBM stacks memory directly on top of ASICs and CPUs rather than beside them on an interposer, promising higher bandwidth and lower latency, but creating power delivery and heat dissipation challenges that Micron plans to address with hybrid bonding, integrated heat spreaders and thermally aware designs. The first vEIM generation targets HBM4-like 2 TB/s bandwidth while consuming less than 1 picojoule per bit. The company is also working with Meta to optimize LPDDR6 for data centers, with about 35 percent lower power consumption expected versus LPDDR5, and plans to develop DDR6 targeting twice DDR5 bandwidth.

In NAND, the G11 (N170) generation will lift active memory layers from 276 to more than 400, introduce wafer-on-wafer bonding, and is expected to double bit density, raise I/O speed by 50 percent and cut data transfer energy by more than 25 percent, with mass production planned for the second half of 2027. Beyond G11, DeBoer said Micron is “really focused on new materials densifying the cell architecture, and continuing to focus on that XYZ scaling going forward.” Two AI-focused NAND architectures are in development: a High-IOPS design based on SLC with small blocks, targeting 25 million to 100 million IOPS, and a High-Bandwidth design exploring TSV-stacked NAND with a logic base die to bring memory closer to compute. DeBoer said: “We do not think placing it along the shoreline of the GPU has merit. Instead, we want to position it closer to the compute itself to take advantage of this high-performance NAND.”

DeBoer said Micron now works with customers from the earliest stages of product definition through joint design, development, validation and volume production, a very different approach from the way the company interacted with customers even three or four years ago. Across its AI co-invention opportunities, he said, Micron is co-imagining, co-designing, co-developing, co-validating and then delivering at scale. The company also expects more than a 10-times improvement in DRAM CMOS logic performance between 2020 and 2030, and its SSD roadmap includes plans for drives with capacities up to 512 TB.