Tesla has disclosed a revamped AI accelerator roadmap that includes renaming its inference chips with ‘SI’ (super intelligence) branding, targeting an 80x performance boost for the sixth-generation accelerator due in 2029–2030, and a shift to a multi-chiplet design with stacked HBM for its next Dojo training chip.
The Elon Musk-led company revealed the updated plans in a recent presentation, shedding light on its chip development efforts. The roadmap shows that the existing HW4 chip, now called SI4, will be followed by the SI5 (40x performance over SI4, due soon) and the SI6, which aims for 80x the compute of today's SI4. The SI6 is estimated at 17,280 to 46,080 TOPS, depending on how baseline performance is measured, and the roadmap lists 144 GB of memory.
A tweet about Tesla’s new labels said US President Donald Trump wants to replace the term ‘artificial intelligence’ with ‘super intelligence’, adding that Elon Musk may already be embracing the new terminology. Musk previously confirmed that SpaceXAI would be rebranded SpaceXSI for the same reason.
Perhaps the most interesting change is in the Dojo training accelerator line. After Elon Musk cancelled the whole-wafer Dojo project in August 2025 and later said SpaceX and xAI would rely solely on Nvidia hardware, the new Dojo D3 has re-emerged with a considerably different architecture. Tesla describes the next-generation Dojo 3 as a chiplet-based design combining 2.5D and 3D packaging with stacked HBM memory, a departure from the original system-on-wafer approach that used distributed on-chip SRAM. The adoption of HBM suggests Tesla intends to substantially increase memory capacity, which modern AI models demand, but introduces different trade-offs in latency, bandwidth, packaging and power. Tesla has not disclosed D3's compute performance, memory capacity, manufacturing process or development schedule. It claims the chip will be optimised for “space, training, and scaling”, pointing to a more conventional accelerator architecture rather than wafer-scale packaging. The D3 is also set to be optimised for extraterrestrial deployments, likely including radiation hardening for select variants.
On the inference side, Tesla has inked a deal with Samsung Foundry to manufacture the SI6 on a 2nm-class process through 2033. However, Tesla does not envision the chip being produced at Terafab using Intel's 14A fabrication process. The SI6 will retain the multi-chip module approach introduced with the SI5, which should help keep packaging costs manageable. The SI5 is expected to consume between 250W and 800W, depending on application. Performance figures for both chips are based on an assumed 216–576 TOPS for the SI4, which Elon Musk has previously said is 3x to 8x more powerful than the HW3 (rated at 72 TOPS).
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Tesla's stated compute performance vs. SI4 by chip generation
x SI4
Performance targets as presented by Tesla; SI4 baseline set to 1x. Source: Tom's Hardware, citing Tesla presentation
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Analysis
Why This Matters
Tesla's chip roadmap directly affects the performance of its Full Self-Driving (FSD) system and future autonomous vehicles, with each generation promising massive leaps in compute
The shift to conventional chiplet designs and HBM memory signals a retreat from exotic wafer-scale approaches, potentially accelerating time to market and reducing cost
The adoption of ‘SI’ branding ties Tesla to the Trump administration's preferred terminology, which could have implications for federal AI policy and procurement
Background
Tesla has been developing its own inference and training chips for years, using them in its vehicles and its Dojo supercomputer. The company's original Dojo D1 relied on wafer-scale integration, placing 25 processors on a single wafer with 11 GB of SRAM. In August 2025 Elon Musk cancelled the whole-wafer Dojo project, and in August 2026 announced that SpaceX and xAI would exclusively use Nvidia hardware. The re-emergence of Dojo D3 with a chiplet design represents a strategic pivot. The SI rebranding follows a November 2026 statement by President Trump that he wants to replace the term ‘artificial intelligence’ with ‘super intelligence’.
Key Perspectives
No other positions are reported in the source.
What to Watch
Whether Tesla discloses Dojo D3's performance figures and manufacturing timeline in future announcements
Whether the SI6's 80x performance target materialises on schedule by 2030, given historic delays in Tesla chip development
Whether the shift from SRAM to HBM for Dojo impacts training throughput for large models, and if Tesla will still pursue any form of wafer-scale integration
12 claims in this story checked against 1 source: 12 supported.
Show each claim
SupportedTesla adopted SI branding for its AI accelerators and set an 80x performance target for its sixth-generation inference chip.Latest from Tom's Hardware: “Tesla has adopted the term "super intelligence" instead of artificial intelligence for its AI accelerators, renaming them with SI monikers.”
SupportedTesla’s updated roadmap moves its next Dojo training accelerator to a chiplet design with stacked HBM.Latest from Tom's Hardware: “Tesla describes its next-generation Dojo 3 (D3) training accelerator as a chiplet-based design that combines 2.5D and 3D packaging technologies with stacked HBM.”
SupportedTesla’s SI6 is targeted to deliver 80x the compute performance of SI4/HW4 and is due in 2029–2030.Latest from Tom's Hardware: “Tesla's 6 th Generation inference accelerator (SI6): 80X compute improvement over HW4”
SupportedThe roadmap labels the existing HW4 chip SI4, with SI5 and SI6 as the next inference chips.Latest from Tom's Hardware: “existing 4 th Generation inference processor ... (which was originally called HW4, then renamed to AI4, then to SI4)”
SupportedSI5 is listed at 40x SI4 performance and is nearing production.Latest from Tom's Hardware: “Performance vs. SI4 — 1X 40X 80X”
SupportedSI6 is estimated at 17,280–46,080 TOPS and the roadmap lists 144 GB of memory.Latest from Tom's Hardware: “we are talking about 17,280 – 46,080 TOPS (trillion operations per second)”
SupportedA tweet about Tesla’s new labels said President Trump wants to replace “Artificial Intelligence” with “Super Intelligence.”Latest from Tom's Hardware: “Then I remembered: President Trump wants to replace “Artificial Intelligence” (AI) with “Super Intelligence” (SI).”
SupportedMusk confirmed SpaceXAI would be renamed SpaceXSI for the same reason.Latest from Tom's Hardware: “Musk recently confirmed SpaceXAI would be redubbed SpaceXSI for the same reason.”
SupportedMusk cancelled the whole-wafer Dojo project in August 2025 and later said SpaceX and xAI would rely solely on Nvidia hardware.Latest from Tom's Hardware: “after Elon Musk cancelled the whole wafer-level Dojo project in August, 2025, and then said SpaceX and xAI would exclusively use Nvidia hardware in August, 2026”
SupportedTesla has not disclosed D3’s compute performance, memory capacity, manufacturing process or development schedule.Latest from Tom's Hardware: “Tesla has yet to disclose D3's compute performance, memory capacity, manufacturing process, or development schedule.”
SupportedTesla says D3 is optimised for “space, training, and scaling”; the source says this probably means radiation hardening for at least select variants.Latest from Tom's Hardware: “it claims that its Dojo D3 will be optimized for 'space, training, and scaling,'”
SupportedTesla has a Samsung Foundry deal to manufacture SI6 through 2033 using a 2nm-class process, and SI6 will retain the MCM approach introduced with SI5.Latest from Tom's Hardware: “Tesla has already inked a deal with Samsung Foundry to make its 6 th Generation inference accelerators through 2033”
