GlobalFoundries has detailed plans for FDX Fusion, a manufacturing process that it says will deliver 7nm-class power and performance using planar FD-SOI transistors and no EUV lithography, with initial customer production targeted for 2028. In an interview with Tom's Hardware, the company's vice president of its FD-SOI business unit, Sudipto Bose, said the process offers 8nm-class logic density and set 2030 as the target for high-volume manufacturing.
The move is a return to 7nm-class performance by a different route, eight years after GlobalFoundries abandoned development of its 7nm FinFET technology. FDX Fusion relies on advanced planar transistors on fully depleted silicon-on-insulator (FD-SOI), strained silicon substrates and aggressive optical patterning, and will be manufactured with deep ultraviolet (DUV) lithography, with extensive multipatterning likely for the most critical layers.
Bose said FDX Fusion's gate density is 14 million gates per square millimeter, the same as today's industry 8nm standard and 2.2 times the density of the current 22FDX and 22FDX+ generations. Tom's Hardware notes that, assuming a two-input NAND gate as the reference, this translates to about 56 million transistors per square millimeter, comparable to Samsung's 8nm-class nodes. At iso performance and iso power with adaptive body biasing enabled, Bose said, FDX Fusion targets 30% higher performance and 40% lower power than the current-generation FDX, with at least 20% improvement for a standard core.
Bose described the technology as aimed at connectivity (Wi-Fi, Bluetooth, cellular and satellite communications), edge processors with on-chip inference, automotive radar, and data-center connectivity, including circuits that amplify weak electrical signals before they reach compute chips. In those data and signal paths, FDX Fusion would be offered alongside GlobalFoundries' silicon-germanium technology. The process also delivers 500 GHz fT/fmax, which Bose said helps radar, connectivity and data-center applications.
The pitch to customers is cost and flexibility. Bose said FDX Fusion avoids the expensive mask sets and EUV tool chains of conventional 6nm and 7nm-class nodes, supporting a much more competitive mask set price and giving customers flexibility in cycle time and in how many locations the company manufactures. The tradeoff is lower transistor density than 7nm-class nodes; Bose said the die size might be bigger, but should be no bigger than today's 8nm designs.
GlobalFoundries has 90-plus customers ramping on its current FDX generation, Bose said. He said the company has customers committed to building chips on FDX Fusion, and that the supply chain leading into companies including BMW, Bosch NXP, Siemens and Tesla had pushed for the technology and supplied requirements. The initial FDX Fusion PDK is planned for mid-2027, and Bose said discussions with major EDA vendors had been under way for roughly six to nine months.
New manufacturing tools will be required, and the announcement coincided with the topping off of GlobalFoundries' Sprint expansion project in Dresden. Bose said the company wants to reuse as much of the front-end transistor tool chain as possible. He said the 2030 high-volume manufacturing target depends on the first applications and customers.
Analysis
Why This Matters
- FDX Fusion is an attempt to offer 7nm-class performance to chip designers who cannot or do not want to pay for EUV lithography, potentially lowering design and manufacturing costs for edge AI, automotive and connectivity chips.
- It is a test of whether planar FD-SOI can remain competitive against FinFET as GlobalFoundries pushes the technology beyond the 22nm class.
- The timeline (PDK in 2027, first customer production in 2028, high-volume manufacturing in 2030) will determine whether GlobalFoundries can convert the customers it says are already pushing for the process into production design wins.
Background
GlobalFoundries abandoned its 7nm FinFET development around eight years ago, according to the interview, and made FD-SOI a focus of its Dresden operations. FD-SOI uses planar transistors built on an insulating layer and supports adaptive body biasing, a technique that changes a transistor's threshold voltage during operation: forward body bias lowers threshold voltage to improve performance, while reverse body bias raises it to cut leakage. FDX Fusion is designed to combine high-density digital logic with RF, analog and embedded memory on one platform.
What to Watch
- The release of the initial PDK in mid-2027 and whether GlobalFoundries publishes contacted gate pitch and metal pitch numbers after first silicon, which Bose said would come in time.
- Whether the major EDA vendors deliver complete digital, analog and RF design flows for FDX Fusion after the PDK.
- Whether first customer production starts in 2028 and high-volume manufacturing follows by 2030, and whether the first 10 engaged customers are edge designs or data-center connectivity designs, as Bose indicated.
Checked
12 claims in this story checked against 1 source: 9 supported.
Show each claim
- Partly supportedThe headline says GlobalFoundries targets production of FDX Fusion in 2028, without specifying that this is initial customer production.Latest from Tom's Hardware: “Anton Shilov: You also mentioned that you plan to begin manufacturing FDX Fusion in 2028. But does this refer to risk production, initial customer production, or high volume manufacturing? Sudipto Bose: Initial customer production.”
- SupportedInitial customer production is targeted for 2028.Latest from Tom's Hardware: “Sudipto Bose: Initial customer production.”
- SupportedFDX Fusion uses planar FD-SOI transistors and does not require EUV lithography.Latest from Tom's Hardware: “Its FDX Fusion process, built on FD-SOI (fully depleted silicon-on-insulator) technology, promises 7nm-class performance using advanced planar transistors, with no EUV lithography necessary.”
- SupportedFDX Fusion aims for 8nm-class logic density.Latest from Tom's Hardware: “GlobalFoundries' FDX Fusion is a new manufacturing technology that promises 8nm-class logic density and 7nm-class power and performance”
- SupportedFDX Fusion aims for 7nm-class power and performance.Latest from Tom's Hardware: “GlobalFoundries' FDX Fusion is a new manufacturing technology that promises 8nm-class logic density and 7nm-class power and performance”
- SupportedHigh-volume manufacturing is targeted for 2030.Latest from Tom's Hardware: “2030 is when we want to get to high-volume manufacturing with FDX Fusion.”
- SupportedGlobalFoundries abandoned development of its 7nm FinFET technology eight years before this report.Latest from Tom's Hardware: “Eight years after GlobalFoundries abandoned the development of its 7nm FinFET technology, the company is preparing to return to 7nm-class performance”
- SupportedFDX Fusion has gate density of 14 million gates per square millimeter, the same as the industry's 8nm standard.Latest from Tom's Hardware: “our gate density of FDX Fusion will be exactly the same as the industry's 8nm standard today. It is 14 million gates per square millimeter”
- SupportedFDX Fusion's density is 2.2 times that of 22FDX and 22FDX+.Latest from Tom's Hardware: “This is 2.2 times more dense than the current generation FDX (22FDX and 22FDX+).”
- SupportedAssuming a two-input NAND gate as the reference, the gate density translates to about 56 million transistors per square millimeter, comparable to Samsung's 8nm-class nodes.Latest from Tom's Hardware: “Assuming he uses a two-input NAND gate as its reference, each gate contains four transistors, which translates to 56 MTr/mm², which is comparable to what Samsung's 8nm-class nodes use.”
- Partly supportedWith adaptive body biasing, FDX Fusion targets 30% higher performance and 40% lower power than current-generation FDX at iso performance and iso power.Latest from Tom's Hardware: “Power -40% ... At iso performance, ABB on for FDX; Performance 30% ... At iso power, ABB on for FDX”
- Partly supportedFDX Fusion avoids the expensive mask sets and EUV tool chains of conventional 6nm and 7nm-class nodes.Latest from Tom's Hardware: “The mask set is costly; the tool chain is costly. The FDX Fusion platform that we've built isn't going to use EUV tools. ... we can support a much more competitive mask set price compared to 6nm.”