Micron has dropped 4F² memory cells from its DRAM roadmap and will instead use wafer bonding, High-NA EUV lithography and new materials to keep scaling memory, with its chief technology officer saying at an event this week that the technology is 'nearing atomic limits.'
Micron has dropped 4F² memory cells from its DRAM roadmap and will instead pursue wafer bonding, High-NA EUV lithography and new materials to keep scaling memory, with its chief technology officer saying the technology is "nearing atomic limits."
Scott DeBoer, president and chief technology and products officer at Micron, said during the company's event this week: "DRAM is nearing atomic limits at this point. Although we have confidence in several more planar nodes, we are very focused on making sure that we introduce 3D DRAM at the optimal time from a cost and performance point of view."
Micron's current 1γ DRAM process is already in high-volume manufacturing. Its successor, 1δ, is scheduled to enter volume production in the second half of 2027 and promises a mid-20% increase in bit density, optimised for future AI memory products including HBM5, vHBM and vEIM.
Wafer bonding will arrive with the 1ε process, which is under development. The company has not disclosed how it intends to implement the technology or what improvements it expects. For subsequent generations, the ζÅ node, Micron's first sub-10nm-class DRAM process, will adopt High-NA EUV lithography, while the ηÅ node will introduce new materials.
For many of its fabrication technologies over the next five to ten years, Micron is collaborating with Albany NanoTech. "Albany NanoTech, our announced focus on advanced lithography [is] really driving High-NA EUV roadmap for DRAM," said DeBoer. "In particular at Albany with our team there, focused on the next five to ten years."
Micron lists two 3D DRAM generations, 3D1 and 3D2, on its roadmap but has not disclosed architectures or launch schedules. DeBoer described 3D DRAM as "a parallel path", shown on the roadmap between the zeta and eta nodes, which the company would implement "in a fashion that is ideal for cost, complexity, and device performance."
The company is also developing vertical high-bandwidth memory (vHBM), which places memory stacks directly on top of processors such as AI accelerators and GPUs rather than beside them. Micron said the approach promises lower latencies and higher bandwidth thanks to shorter connections, but creates significant thermal challenges and limits the number of stacks that can be integrated on an ASIC. It expects vHBM to complement conventional HBM, which will continue to provide most of the memory capacity in AI accelerators.
Vertical edge inference memory (vEIM) shares vHBM's architectural and packaging characteristics but targets energy efficiency for edge AI processors in autonomous vehicles, robotics and other power-constrained devices. Even the first generation targets 2 TB/s bandwidth at 1pJ/bit energy, in line with what HBM4 currently offers.
Both vertical architectures will require advanced packaging, particularly hybrid bonding, and Micron is developing specialised heat-spreading structures to transfer heat from memory base dies through the DRAM stacks. The company has not disclosed when vHBM, vEIM or custom HBM (cHBM) implementations will enter commercial production. It said the work reflects a shift in which memory performance depends increasingly on advanced packaging and closer integration with processors, turning memory from a commodity into a critical ingredient of ASIC design.
Analysis
Why This Matters
- DRAM is the working memory inside every computer and data centre; the techniques Micron chooses will help determine memory density, cost and energy use as conventional planar scaling slows.
- Memory placed directly on top of processors could change how AI accelerators and edge devices are built, making packaging and thermal management as important as lithography.
- Treating memory as a custom element of chip design rather than a commodity could reshape how DRAM makers and processor designers collaborate.
Background
DRAM's economics have historically depended on shrinking the memory cell on a flat, planar die generation after generation to raise density and cut cost per bit. As those shrinks approach physical limits, memory makers are looking at stacking cells vertically and pulling memory closer to processors, following the pattern the flash memory industry adopted with 3D NAND. Micron's roadmap mixes several more planar nodes with parallel work on 3D DRAM and on packaging memory on top of processors, with the company saying it will switch to 3D structures only when they offer the right balance of cost, complexity and performance.
What to Watch
- Micron has not said how wafer bonding will be implemented in the 1ε process or what gains it expects; details on the approach would clarify how central packaging has become to DRAM scaling.
- The second half of 2027, when the 1δ process is scheduled to enter volume production, optimised for AI memory products including HBM5, vHBM and vEIM.
- Launch timing for vHBM, vEIM and cHBM products, which would signal how quickly memory-on-processor designs move from the roadmap into commercial hardware.
Checked
7 claims in this story checked against 1 source: 2 supported.
Show each claim
- SupportedThe headline says Micron is to adopt wafer bonding and High-NA EUV as DRAM nears atomic limits.Latest from Tom's Hardware: “Micron intends to introduce wafer bonding with its upcoming 1ε DRAM process technology and adopt High-NA EUV lithography for subsequent generations. ... “DRAM is nearing atomic limits at this point,” said Scott DeBoer”
- Partly supportedThe opening says Micron will use wafer bonding, High-NA EUV and new materials to keep scaling memory.Latest from Tom's Hardware: “Micron intends to introduce wafer bonding with its upcoming 1ε DRAM process technology and adopt High-NA EUV lithography for subsequent generations.”
- SupportedThe opening attributes the statement that DRAM is nearing atomic limits to Micron’s CTO at the company’s event this week.Latest from Tom's Hardware: ““DRAM is nearing atomic limits at this point,” said Scott DeBoer, president and chief technology and products officer at Micron, during the company’s event this week.”
- Partly supportedWafer bonding will arrive with the 1ε process.Latest from Tom's Hardware: “Micron plans to introduce wafer bonding with its 1ε process, which is currently under development.”
- Partly supportedThe first-generation vEIM targets 2 TB/s at 1 pJ/bit.Latest from Tom's Hardware: “even the 1st Generation vEIM targets formidable 2 TB/s bandwidth at <1pJ/bit energy”
- Not in the sourcesMicron said vHBM promises lower latencies and higher bandwidth because of shorter connections.Latest from Tom's Hardware: “This approach promises substantially lower latencies and higher bandwidth thanks to shorter connections.”
- Not in the sourcesMicron said the work reflects a shift toward memory performance depending increasingly on packaging and closer processor integration.Latest from Tom's Hardware: “What is important about the development of such types of memory is that it indicates that future improvements in memory performance will increasingly depend on advanced packaging and closer integration with processors”
